I am a skilled VLSI Design Engineer with 5 years of experience in the field. I have a deep passion for creating innovative solutions and pushing the boundaries of digital design.

Throughout my career, I have been actively involved in multiple domains like SoC RTL design (development and standalone validation of DFD feature for SoC systems), Standard cell library characterization and modeling (generation and delivery of liberty and power analysis collaterals). My expertise lies in Digital Design, RTL Coding and Scripting. I have a strong understanding of industry-standard design methodologies and tools, and I am well-versed in hardware description languages such as Verilog(IEEE-1364) and System Verilog(IEEE-1800).

I have successfully contributed to the development of complex System-on-Chip (SoC) designs, working closely with cross-functional teams and collaborating with architects, post-silicon engineers, and verification engineers to ensure seamless integration and functionality. I thrive in fast-paced environments, tackling challenging design problems, and delivering high-quality results within tight schedules.